Call for Collaboration: Seeking Public UVM Environments for Verilator 5.0+ Porting

The transition of SystemVerilog UVM environments to open-source simulators presents specific technical challenges. While Verilator 5.0+ has expanded support for various SystemVerilog constructs, the industry still lacks a documented and repeatable path for certain UVM-specific behaviors. In parallel, we aim to curate a public vault of UVM repositories that have been successfully ported to Verilator.

AsFigo is initiating a collaborative effort to document these gaps, and we are looking for engineers, researchers, and students to contribute original UVM codebases to this effort. Link to Google Form: Submit Your code base

The Technical Focus

This effort intentionally moves beyond minimal or illustrative examples. We are seeking unique, original UVM implementations that reflect realistic UVM environments and non-trivial SystemVerilog usage found in real-world verification flows.

• Infrastructure Components: Memory controllers, DMA engines, or asynchronous FIFOs
• Management Logic: Multi-agent arbiters (priority, round-robin) or interconnect fabrics
• Standard Protocols: Original implementations of AHB, APB, SPI, or I2C with custom layering

Objectives: Industry, Academia, and AI

This is a data-driven effort intended to broaden access to realistic verification tooling:

• Industry: Identifying a viable, low-cost path for UVM-based verification on Verilator
• Academia: Providing executable UVM environments for research without reliance on commercial simulator licenses
• AI/ML Development: Building executable open-source datasets required to train and evaluate future AI-driven verification agents

Submission & Collaboration Guidelines

We invite submissions of original UVM work developed during individual learning, research, or experimentation.

• Public Repositories Only: No proprietary or restricted code
• Artifacts: A file list (.f) and a reference log from a commercial simulator are strongly preferred to establish a functional baseline

Logistics and Selection

This is a volunteer-led, best-effort initiative by AsFigo. Submissions will be prioritized based on technical complexity and the uniqueness of the verification logic.

Link to Google Form: Submit Your code base

• Milestone: Initial findings and porting strategies may be shared at the March 5th “Chips @ Dojo” event
• Real-Time Sync: Contributors may opt in to a WhatsApp group for collaborative debugging and workaround discussions.