Join Us in Cambridge - Advancing Chip Verification with UVMLint & SVALint

AsFigo invites you to our next technical session, focused on enabling semiconductor design teams to adopt open-source EDA tools—especially for testbench linting workflows.

📍 Event: UVMLint & SVALint – Enablers to Move Your Chip Design Ahead
📅 Date: Friday, June 27, 2025
🕙 Time: 10:00 AM to 12:00 Noon (UK Time)
📌 Location: Wellington House, East Road, Cambridge, CB1 1BH, United Kingdom
☎ Phone: +44 1223 451000
🌐 Format: Hybrid (in-person & remote via Microsoft Teams)
💡 Cost: Free (registration required - https://forms.gle/upzLGyWJbRnbgRzU7)

After a successful SVALint session in Reading, UK, we’re bringing this discussion to Cambridge—one of the UK’s most active semiconductor hubs. This event is geared toward engineers working in UVM based verification, formal verification, and testbench architecture using UVM and SVA.

Agenda Highlights

  • Upgrading to IEEE 1800.2 UVM with linting-guided workflows
  • Using a custom BYOL (Build Your Own Linter) to estimate and plan migration efforts
  • Establishing UVM coding guidelines tailored to project and team needs
  • Extending SVALint for EBMC: validating SVA compatibility with an open-source formal verification tool

We have an exciting set of contributions from speakers across the UK, Europe, India, and the US (tentative), bringing practical insights from real-world deployments.

Join Us

Whether you're exploring testbench linting, formal verification with open source tools, or migration paths to IEEE 1800.2 UVM, this session aims to provide technically grounded insights and tools you can use immediately.

Note: This is a free event, but registration is mandatory (Link: https://forms.gle/upzLGyWJbRnbgRzU7) —especially if you plan to attend in person. A Microsoft Teams link will be shared with registered online attendees closer to the event date.

We look forward to meeting you in Cambridge—or online.

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