Technical Meetup: Open Source Chip Design and Verification, Jan 9, Hyderabad

Technical Meetup: Open Source Chip Design and Verification

AsFigo is hosting a technical session dedicated to the advancements in open-source hardware design and verification. Register for the Event 

This session is designed for engineers and practitioners looking to integrate modern automation and open-source methodologies into their silicon workflows.

The discussion will center on the practical application of GenAI in hardware development, alongside a deep dive into specialized linting tools including SVALint, FPGALint, and UVMLint.

Event Details

  • Date: Friday, January 9th, 2026
  • Time: 1:00 PM – 5:00 PM IST
  • Format: Hybrid (In-person and Remote)
  • Venue: Acendia Arc, SY NO.12, White Field, Lingampalli, Serilingampally, Hyderabad, Telangana 500019

Agenda & Topics

  • GenAI in Silicon: Exploring the role of Generative AI in RTL generation and verification productivity.
  • Advanced Linting: Best practices for SystemVerilog and UVM using SVALint and UVMLint.
  • FPGA Workflows: Utilizing FPGALint to ensure design robustness and synthesizability.
  • Open Source EDA: Navigating the ecosystem of open-source tools for modern chip design.

Registration

This is an open invite to the technical community. However, physical attendees must register by January 6th to ensure building access and logistical support.

For those attending remotely, connection details will be shared with registered participants prior to the event.

Register for the Event

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