Contributing to UVM-MS LRM through public review prcoess

Our Director of Verification, Ajeetha Kumari took part in offering her review comments based on her decades of AMS design verification experience to Accellera's UVM-MS standard. 

Overall, our focus is on clarity, correctness, good coding practices, and ensuring UVM-MS follows standard verification methodologies.   


  1. Clarifications and Expansions

    • Suggested explicitly stating IEEE 1800.2 UVM version to avoid ambiguity.
    • Asked whether VHDL should also be considered in addition to SystemVerilog.
    • Recommended good coding guidelines for UVM-MS lint rules.
    • Pointed out grammatical issues, such as removing unnecessary "s" in certain words.
    • Suggested formatting improvements, such as italicizing specific terms.

  2. Code and Implementation Improvements

    • Recommended ensuring all UVM components/agents are in separate packages for better reuse.
    • Questioned the lack of UVM factory registration for some proxy classes.
    • Suggested adding function prototypes (like new()) for better clarity.
    • Advised on using absolute paths carefully, as they may cause reuse issues.
    • Recommended avoiding macros in certain places and explicitly declaring virtual functions.

  3. Conceptual Enhancements

    • Proposed adding examples for UVM-MS scoreboard for completeness.
    • Suggested ensuring naming conventions for UVM-MS components (e.g., using _ms_ in names).
    • Asked whether methods or patterns should be used in certain parts of the document.


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