Unlocking RTL Quality with Open Source Technologies - online event!
Unlocking RTL Quality with Open Source Technologies: A Must-Attend Event for Chip Designers
In the ever-evolving world of chip design, verification bottlenecks and RTL quality remain critical challenges. Open-source tools and AI-driven approaches are revolutionizing the way we optimize and validate hardware designs. Join us for an exciting technical event that brings together industry experts, FPGA specialists, and innovators who are pushing the boundaries of open-source EDA.
Why Attend?
This event is designed for verification engineers, FPGA designers, and AI-driven hardware developers eager to explore new methodologies in SystemVerilog linting, FPGA coding best practices, and AI applications in chip design.
Agenda Highlights (IST - India, UTC +5:30)
2:00PM - 2:30PM
SV Testbench Constraints Can Blind You – Build Your Guards - Nambi JU, CTO, Lyle Technologies
2:30PM - 3:00PM
UVMLint – a BYOL: UVM System Verilog Linter - Muthukumarar Vaithianathan, Semiconductor Technologist, San Diego, CA, USA
3:00PM - 3:30PM
An Industry Perspective on Unlocking RTL Quality with Open Source Lint Tools - Narahari TR
3:30PM - 3:40PM
Tea Break
3:40PM - 4:10PM
FPGAs in Bringing Code Novelties Using Open Source & Customized Linting - V.P. Sampath, Founder, Bharath Semiconductor Society, FPGA Expert
4:10PM - 4:30PM
Enabling AI in Chip Design through Open Source - Marmik Soni & Mike Bartley, Senior Design Lead, SVP Tessolve
4:30PM - 4:50PM
yoYOLint - RTL Linter for SystemVerilog Synthesis Tailored for Yosys - Saanvi Pradhan, High School Student, Austin, USA
4:50PM - 5:00PM
Q&A & Networking
How to Participate
Attendance: This is a hybrid event, and participation is strictly via online registration.
Join Virtually: The event will be streamed live via MS Teams. You can join the event from anywhere by following the provided link.
Registration: Please register in advance to confirm your participation and receive the online event link.
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