Open Source Chip Design and Verification Event: Unlocking the Future of Semiconductor Innovation

The semiconductor industry is undergoing a transformation, with open-source tools playing a pivotal role in shaping the future of chip design and verification. On January 30, 2025, AsFigo and VerifWorks will host the Open Source Chip Design and Verification Event, a hybrid event offering a platform to explore how open-source technologies are driving innovation in the semiconductor industry.

📅 Event Details

  • Date: January 30, 2025
  • Time: 2:00 PM to 5:00 PM
  • Location: Virtual (via MS Teams)

This event will focus on the application of open-source tools for front-end design and verification in semiconductor chip development. The sessions will explore tools, techniques, and real-world applications that leverage open-source solutions to improve the quality and efficiency of chip design and verification workflows.

📋 Agenda

The event features key speakers from various domains of semiconductor technology who will discuss important aspects of open-source chip design and verification:

  1. "SV Testbench Constraints Can Blind You, Build Your Guards!"
    Nambi, CTO, Lyle Technologies
    Nambi will discuss the challenges of managing SystemVerilog (SV) testbench constraints and the importance of building effective guards to prevent issues in verification. His session will focus on how such constraints can obscure problems in the testbench, and how open-source tools can help address these issues in more efficient ways.
  2. "UVMLint – a BYOL: UVM System Verilog Linter"
    Muthukumaran Vaithianathan, Semiconductor Technologist, San Diego, CA, USA
    Muthukumaran will introduce UVMLint, an open-source UVM SystemVerilog linter that helps identify common issues in UVM-based verification environments. He will demonstrate how UVMLint can improve code quality, enforce design consistency, and enhance the overall verification process.
  3. "An Industry Perspective on Unlocking RTL Quality with Open Source Lint Tools"
    Narahari, Senior Vice President at SignOff Semiconductors (ex-Intel, ex-LSI)
    Narahari will discuss the role of open-source lint tools in improving RTL quality and how they can be integrated into the design flow to catch errors early in the development process. He will provide an industry perspective on the impact of these tools on streamlining workflows and improving efficiency.
  4. "FPGAs in Bringing Code Novelties Using Open Source, Customized Linting"
    V.P. Sampath, Founder of the Bharath Semiconductor Society, FPGA Expert
    V.P. Sampath will explore how FPGA-based designs can benefit from customized linting solutions. His session will cover how tailored linting tools are being applied to FPGA workflows to enhance performance, uncover hidden issues, and streamline code development.
  5. "yoYOLint - RTL Linter for SystemVerilog Synthesis Tailored for Yosys"
    Saanvi Pradhan, USA
    Saanvi will introduce yoYOLint, an RTL linter designed for SystemVerilog synthesis in the Yosys open-source synthesis tool. She will discuss how yoYOLint can be used to check and improve the quality of RTL code before synthesis, ensuring smoother integration and fewer errors downstream.

🔗 How to Participate

Attendance: This is a hybrid event, and participation is strictly via online registration.

Join Virtually: The event will be streamed live via MS Teams. You can join the event from anywhere by following the provided link.

Join the event via MS Teams

Registration: Please register in advance to confirm your participation and receive the online event link.

Event Registration

Conclusion

The Open Source Chip Design and Verification Event offers an essential platform for those involved in chip design, verification, and semiconductor technology to gain insights into the latest developments in open-source tools. From SystemVerilog testbench constraints to FPGA-specific linting, the event will cover a broad range of topics that are critical for optimizing chip design workflows.

If you're looking to improve your RTL design and verification processes, stay ahead of the curve with open-source tools, and connect with industry professionals, this event is not to be missed.

We look forward to your participation on January 30 through the online platform.

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