WOSET 2024: Spotlight on yoYoLint - An Open-Source SystemVerilog RTL Linter

As open-source electronic design automation (EDA) tools continue to grow in popularity, events like WOSET (Workshop on Open-Source EDA Technology) have become essential for showcasing community-driven advancements. The 2024 edition of WOSET features an exciting lineup, including yoYoLint—a new open-source SystemVerilog RTL linter designed for Yosys. Built on AsFigo’s innovative "Build Your Own Linter" (BYOL) model, yoYoLint adds a much-needed layer of quality control to open-source HDL flows, addressing the often-overlooked process of HDL linting.

Understanding the Role of HDL Linting in EDA

Linting is a critical phase in hardware description language (HDL) design flows, helping enforce design rules, style guides, and best practices to ensure code quality. A robust HDL linter for SystemVerilog helps identify errors early, such as unused variables, unsupported constructs, potential race conditions, or missing sensitivity list items, enabling teams to produce clean, consistent, and maintainable code.

yoYoLint: Empowering Designers with Custom Linting



Yosys has been a key player in advancing open-source EDA, with strengths in synthesis, optimization, technology mapping, and design transformations. While Yosys focuses on synthesis, its error messages can sometimes be brief, offering limited guidance on specific code issues. This is where yoYoLint adds significant value: it provides clear, user-friendly diagnostics to help designers catch and resolve issues early. By linting with yoYoLint, users can ensure their code is well-formed before Yosys synthesis, enhancing productivity and making the flow more efficient.

yoYoLint represents a major step forward in open-source EDA tooling, offering designers the flexibility to create and customize linting rules specifically for SystemVerilog RTL designs. Based on AsFigo’s BYOL model, yoYoLint offers a framework for implementing and enforcing design standards that are easy to modify and expand.

Key Features of yoYoLint

  • Independent of Yosys’s Limitations: yoYoLint is designed to complement Yosys but operates independently of its synthesis capabilities, meaning it supports the full SystemVerilog LRM without being restricted by Yosys’s own SystemVerilog subset. This ensures comprehensive language coverage and a smooth fit into open-source EDA workflows.
  • Customizable Rule Sets: Designers can define their own linting rules using a simple and expressive syntax, allowing for enforcement of project-specific or organization-wide design standards.
  • SystemVerilog Support: Unlike many open-source linters focused on Verilog, yoYoLint provides robust support for SystemVerilog constructs and semantics. Built on top of the Slang parser, yoYoLint offers extensive language feature coverage.
  • Extensibility: The BYOL model enables easy extension of yoYoLint’s capabilities, allowing the community to contribute new rules and checks.

Technical Deep Dive

Rule Definition

yoYoLint uses a Python to define linting rules, making it straightforward for users to create checks for specific constructs or patterns. For example, a rule might ensure we don't use local enum definitions as Yosys does not support the same and also it is bad for reuse. Below code snippet implements the same:

# Saanvi added
def NO_ENUM_DEF_IN_MOD(lvCuScp):
    if (lvCuScp.kind.name == 'ModuleDeclaration'):
        for lv_mod_mem_i in lvCuScp.members:
            if (lv_mod_mem_i.kind.name == 'DataDeclaration'):
                if (not hasattr(lv_mod_mem_i.type, 'keyword')):
                    return
                if (lv_mod_mem_i.type.keyword.valueText.strip() == 'enum'):
                    lv_tdef_s = lv_mod_mem_i.__str__()
                    msg = 'A local enum was found inside a module'
                    msg += ' This prevents reuse as the enum is module only'
                    msg += ' Also Yosys does not support this yet (NYS).'
                    msg += ' Please create a typedef in a package'
                    msg += ' and import that package inside the module'
                    msg += str(lv_tdef_s)
                    lvRID = 'NO_ENUM_DEF_IN_MOD'
                    yYLMsg(lvRID, msg)

AST Traversal

yoYoLint relies on Slang’s abstract syntax tree (AST) representation of SystemVerilog code. Using Slang’s open-source parser and Python binding, yoYoLint traverses the AST to apply defined rules efficiently, allowing for high accuracy in linting.

Community Impact and Future Directions

yoYoLint’s debut at WOSET 2024 is expected to generate substantial interest within the open-source EDA community. Its flexibility, along with seamless Yosys integration, makes it a valuable tool for improving RTL code quality and enforcing consistent design standards. Future developments for yoYoLint include:

  • Expanding the rule library with contributions from the community
  • Increasing SystemVerilog language coverage
  • Integrating with additional open-source EDA tools
  • Developing a graphical interface for easier rule management

Conclusion: The Future of Open-Source HDL Linting

yoYoLint marks an important advancement in open-source HDL quality assurance, bringing comprehensive SystemVerilog linting capabilities to the Yosys ecosystem. Leveraging AsFigo’s BYOL model, yoYoLint provides a customizable, extensible approach to linting that enables developers to set and maintain high standards. As open-source solutions gain traction in EDA, tools like yoYoLint highlight the importance of a robust toolchain focused on code quality as well as functionality.

With yoYoLint, designers and teams gain access to a powerful, open-source linter that enhances the HDL design experience, ensuring quality and maintainability are foundational to the open-source hardware movement.

Comments

Post a Comment

Popular posts from this blog

Opensource testbench generator for VHDL designs, OSVVM included!

Image
VHDL holds a prominent position in the world of FPGA design, particularly within the military, aerospace, and defense sectors. It serves both as a Register Transfer Level (RTL) design language and as a tool for creating testbenches. The availability of open-source simulators, such as GHDL and NVC, alongside numerous free FPGA simulators and synthesis tools, has provided FPGA designers with a significant advantage over their SystemVerilog counterparts. While the Universal Verification Methodology (UVM) is widely adopted among SystemVerilog users, VHDL practitioners have traditionally relied on various homegrown methodologies and frameworks. Recently, however, off-the-shelf methodologies and frameworks such as OSVVM, UVVM, and VUnit have become available to VHDL users. Each of these options presents different levels of complexity, allowing users to choose the one that best meets their needs. Despite these advancements, the development of open-source utility tools supporting the latest me...
Read more

Porting a complete UVC to Verilator + UVM - an anecdote!

Image
 So, here we are on Day-1 of UVM + Verilator becoming available to the public, start of democratizing chip design verification. In case you just woke-up/started on this topic, read the release of UVM + Verilator with some intricate details on the challenge on the way by Antmicro via:  https://antmicro.com/blog/2023/10/running-simple-uvm-testbenches-in-verilator/  Awesome work by the folks at Antmicro and fantastic support by the ecosystem specifically Western Digital, kudos!  At AsFigo , we are committed to fueling open-source driven chip design and verification. So we took this opportunity to port a commercial-grade UVC (Universal Verification Component or a Verification IP) and ported it to compile and run on Verilator. Below are our reflections from this experiment. Get in touch with us to discuss how AsFigo can help your VIPs and testbenches to be ported to opensource EDA.  Case study: VLBus - a simple peripheral bus intended for write/read to configuration...
Read more

Meet the team behind SystemVerilog Assertions Handbook

Image
The SystemVerilog Assertions Handbook The SystemVerilog Assertions Handbook is a popular publication in the field of hardware design and verification. Authored by Ben Cohen, Ajeetha Kumari, Srinivasan Venkataramanan, and Lisa Piper, it became the world’s first book solely dedicated to SystemVerilog Assertions (SVA) when it was first published in 2005. At a time when SystemVerilog was gaining widespread acceptance, the authors recognized the need for a focused resource that could demystify assertions and provide engineers with practical insights into their use in modern verification flows. Now in its fourth edition, the handbook has evolved in tandem with advancements in the SVA standard, making it an indispensable reference for both beginners and experienced verification engineers. What sets this book apart is its combination of theory and practical examples, offering real-world insights into the effective use of SVA for improving design verification quality....
Read more