AsFigo Instance Extraction Utility ($afPrHier)

The AsFigo Instance Extraction Utility ($afPrHier) is a Verilog Procedural Interface (VPI) app designed to automate the extraction of instance hierarchy data in Verilog simulations. It provides an efficient solution for analyzing and documenting the structural organization of Verilog designs, particularly in complex simulations.

Purpose and Benefits

Objective

$afPrHier simplifies the process of collecting and documenting hierarchical relationships among modules and their instances in a Verilog simulation. It automates this task to reduce manual effort and potential errors.

Features

  • Automated Hierarchy Extraction: Gathers all module-instance relationships in a design and organizes them in a structured format.
  • CSV-Based Reporting: Outputs hierarchy details in output_hier_info.csv with two essential columns:
    • Module Name
    • Instance Name
  • Simulation Integration: Operates as a VPI system task, enabling automatic execution at simulation startup.

How It Works

Integration with Simulation Environment

The utility is compiled into a VPI shared library (e.g., .so on Linux) that is dynamically loaded into the simulator. This allows $afPrHier to traverse the module hierarchy of a running simulation and log relevant data.

Usage in a Verilog Testbench

To invoke the utility, include the $afPrHier system task in your testbench code. For example: 

        
module testbench;
  initial begin
    $afPrHier; // Triggers the hierarchy extraction
  end
endmodule

Output

Upon execution, $afPrHier generates a CSV file named output_hier_info.csv. This file contains a tabular representation of the design hierarchy:

Module Instance Name
module_name instance_name

Simulation Workflow

  1. Compile the VPI Library: Create a shared library (afPrHierVpi.so) using a C++ compiler such as gcc, linking it with the simulator's VPI headers.
  2. Load the Library in the Simulator: Specify the library in the simulator’s command line. For example: 
                    vsim -pli afPrHierVpi.so <your_verilog_testbench>
  3. Run the Simulation: When $afPrHier is invoked in the testbench, the utility iterates through the module hierarchy and logs the data into the CSV file.
  4. Examine the Output: Access the generated output_hier_info.csv to analyze the hierarchy.

Error Handling

The utility includes built-in mechanisms for handling common runtime issues, such as:

Error Code Description
ERR_FILE_OPEN The output CSV file could not be created or opened.
ERR_MOD_ITERATION Failed to iterate through module instances.
ERR_SYSTF_CALL Error while accessing the $afPrHier system task.
ERR_SYSTF_USAGE $afPrHier invoked with incorrect or extra arguments.

So, give it a try and let us know if you have any feedback! 

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