Waves2UVM - an opensource bridge between Formal & UVM

Waves2UVM is an app within the Go2UVM ecosystem that aids in the automatic generation of UVM testbenches from waveform data. This is especially valuable for engineers aiming to accelerate the design verification process of complex hardware systems. The tool works by translating waveform dumps (which capture signal behavior during simulations) into UVM verification components, thereby eliminating the manual coding typically required for testbench creation.



The key advantage of Waves2UVM is its ability to work with formats like WaveDrom, offering a streamlined path from a structured, waveform data to a functional UVM testbench, which can be utilized within broader UVM verification flows. This improves productivity in hardware verification by reducing errors introduced during manual coding and speeding up the overall verification cycle.

A recent customer usage of this handy technique deals with reproducing Formal Verification traces in simulation world. As Formal Verification tools such as Siemens EDA's Questa OneSpin Model Verifier (MV) are used heavily in domains such as automotive chip design verification, a key bridge is necessary to port traces produced by OneSpin in a UVM environment. At AsFigo, we leveraged on our founders' earlier work on Waves2UVM to enhance and address this challenge. Listen to Ajeetha Kumari elaborating on these more pragmatic uses of formal verification traces at next week's Osmosis 2024 event being held at Munich, Germany. 

Go2UVM itself provides various macros, add-on layers and apps, including Waves2UVM, that help users quickly adopt and implement the Universal Verification Methodology (UVM), an industry-standard framework for verifying semiconductor designs. This makes Go2UVM a valuable resource for both novice and experienced verification engineers working with UVM in SystemVerilog environments.



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