BYOL - a custom linter for Yosys; yoYoLint

yoYoLint is an opensource linter being developed to check SystemVerilog (SV) RTL code for compatibility with the Yosys open-source synthesis tool. Yosys, a popular, opensource  hardware description language (HDL) synthesis tool, has limited SystemVerilog support and often produces cryptic errors for unsupported constructs. As Yosys does not provide a comprehensive list of unsupported features, yoYoLint becomes essential in preemptively catching these issues before synthesis.

Unlike off-the-shelf EDA tools, yoYoLint follows the BYOL (Build Your Own Linter) model, a concept proposed by AsFigo. This allows developers to customize and adapt the tool to their specific design needs and Yosys synthesis environment.

Key Features

  • Yosys-Specific Checks: yoYoLint flags unsupported SystemVerilog features, such as complex data types, advanced procedural blocks, and unsupported constructs in Yosys.
  • RTL-Focused: Analyzes common RTL patterns, identifying issues such as improper clocking, unsupported register inference, and non-synthesizable logic.
  • Pre-Synthesis Validation: Ensures SystemVerilog code adheres to Yosys-supported syntax and semantics, preventing synthesis failures.
  • Customizable Linter: Adopting the BYOL model, yoYoLint allows users to adapt linting rules based on their unique design and workflow requirements.

Sample Lint Rules

  • Package Limitations: Detects SystemVerilog packages that are not supported by Yosys, helping avoid issues where package-scoped variables or types cause synthesis failures.
  • Lack of Multidimensional Array (MDA) Support in Ports: Flags cases where multidimensional arrays are used in module ports, as Yosys has limited support for these in synthesis.
  • Unsupported $clog2 Function: Detects the use of the $clog2 function, which is not fully supported in Yosys, to prevent errors in code that relies on this calculation for sizing arrays or counters.
  • Limitations in int Usage: Identifies places where the int data type is used in contexts not supported by Yosys, ensuring that incompatible constructs are flagged before synthesis.

Benefits

  • Early Error Detection: Identifies unsupported constructs before running Yosys, preventing cryptic and time-consuming errors during synthesis.
  • Code Quality: Enforces Yosys-compatible RTL design practices, improving maintainability and synthesis-readiness.
  • CI/CD Integration: Since yoYoLint is free and open-source, it can be integrated into CI/CD pipelines, allowing automated checks to be performed early in the design process. This ensures continuous adherence to Yosys constraints.
  • Handle Yosys’s Limited Documentation: Since Yosys lacks a comprehensive list of unsupported SystemVerilog features, yoYoLint is crucial for catching problematic constructs before synthesis.
  • Efficient Workflow: Reduces iteration time by catching issues early, streamlining the synthesis process for Yosys users.

yoYoLint, with its customizable BYOL model, is a valuable tool for developers using Yosys for SystemVerilog RTL synthesis. Its flexibility in handling unsupported features and integration with CI/CD pipelines ensures smoother, more efficient synthesis workflows.

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