A Specman/E (IEEE 1647) port to MathLib

IEEE 1647 - e Language (Specman) & MathLib

We at AsFigo have deep expertise in multitude of design verification and modeling techniques including IEEE 1647 e language. Our core team has contributed to development of the IEEE standard, presented at various industry events on Specman such as DAC. Fast forward to 2024 - we were approached by a customer to make their reference models run with native E. Erstwhile their reference models were DSP algorithms modeled in Matlab. While E language does provide similar functions, they are not always 100% compatible especially around negative values, corner cases, rounding limits etc. thereby leading to customers retaining Matlab + Specman in their flows. Based on AsFigo's MathLib success with SystemVerilog & VHDL (A brief report of that below), we did a porting of MathLib basic features to IEEE 1647 e. We will be thrilled to opensource a basic version of this implementation shortly, so watch out our GitHub repositories! Meanwhile if you have a legacy Specman code that needs maintenance/upgrading/porting, give us a call!  2023 and FPGA World 2023

Overview

In 2023, AsFigo showcased its advanced mathematical library, MathLib, at many key industry events: the Design Automation Conference (DAC) and FPGA World in Stockholm & ORConf Munich. These presentations highlighted MathLib's capabilities in enhancing ASIC & FPGA-based designs and received significant attention from the engineering and academic communities.

DAC 2023

  • Event: Design Automation Conference (DAC)
  • Location: San Francisco, USA
  • Date: June 2023

Key Highlights

  • Work-in-Progress Poster: AsFigo presented a work-in-progress poster detailing the capabilities of MathLib. This session allowed for direct feedback from industry professionals and academics, fostering an environment of collaboration and innovation.
  • Technical Demonstrations: The presentation included live (in private) demonstrations of MathLib, showcasing its ability to assist in ASIC & FPGA designs.
  • Industry Engagement: AsFigo's poster attracted numerous visitors, providing opportunities to discuss the practical applications of MathLib and its integration into existing FPGA projects. Watch a brief video: https://youtu.be/1SZ4F2LW61E 

FPGA World 2023

Key Highlights

  • Collaboration with VUnit: The presentation at FPGA World was done in collaboration with VUnit, emphasizing the integration of MathLib with VUnit's testing framework to streamline the verification process in FPGA development.
  • Customer Success Stories: Real-world case studies were presented, illustrating how companies have successfully implemented MathLib to enhance their FPGA-based projects, resulting in improved efficiency and reduced development times.

ORConf 2023

  • Event: ORConf
  • Location: Munich, Germany
  • Date: September 2023

Key Highlights:

  1. Presentation by Deepa Palaniappan: Deepa Palaniappan from AsFigo delivered a presentation on MathLib, focusing on its role in open-source silicon design and its integration with various verification tools. This talk was well-received, highlighting the practical applications and benefits of MathLib in real-world projects.
  2. Community Engagement: ORConf attendees, including open-source hardware developers and EDA tool users, engaged with AsFigo's team, discussing potential collaborations and future enhancements to MathLib​ (ORConf)​​ (ORConf)​.
  3. A recorded version is at: https://youtu.be/KJHWmYgdT90 

Basis of MathLib

MathLib is a MATLAB-compatible library written in native SystemVerilog and VHDL, providing a cost-effective alternative to MATLAB. By offering a native implementation that is 100% compatible with MATLAB, MathLib allows users to utilize reference models without incurring the high license costs associated with MATLAB. This compatibility ensures that engineers can seamlessly transition their MATLAB-based workflows to an FPGA environment, leveraging the full capabilities of SystemVerilog and VHDL for optimized performance.

Conclusion

AsFigo's presentations at DAC 2023 and FPGA World 2023 successfully demonstrated the advanced capabilities of MathLib in the context of FPGA design and development. The events provided valuable platforms for engaging with industry experts, showcasing real-world applications, and highlighting the collaborative potential of integrating MathLib with other industry tools like VUnit. These presentations reinforced MathLib's position as a crucial tool for optimizing FPGA designs and driving innovation in the field.

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