uFC - Our RISC-V verification solutions - a sneak preview

RISC-V – a name that sparks innovation all across the globe! Recent market survey by SHD indicates RISC-V industry to touch $92B by 2030 (The SHD Group Has Released a Complimentary Version of the 2024 RISC-V Market Analysis Report Containing Current Market Data and Future Projections | Newswire). 

Credits: SHD


We at AsFigo are driven by opensource and help our customer adopt the same in chip design. One challenge that many RISC-V verification teams are facing is the long coverage closure cycles at RTL stage. This is primarily due to the long simulation cycles when RTL along with RISC-V assembly code is simulated using a typical event-driven simulator. We have recently helped customers with this challenge by leveraging on opensource RISCV-DV framework to measure functional coverage of uCode using ISS (Instruction Set Simulator) and also with a thin HDL-like testbench. Below is a summary of results of this approach.



Do join us at RISC-V Summit Europe 2024 at Munich to learn more!






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