Opensource VHDL simulator - NVC, installing on WSL-Ubuntu

We at AsFigo AsFigo love Opensource. Off late we have been helping some European customers adopt modern verification techniques using VHDL. As a byproduct we have been building a Python based VHDL utility to generate a generic testbench based on OSVVM. While doing so, our team stumbled upon few subtle simulator issues, see:

https://osvvm.org/forums/topic/sbrd-package-issue-with-modelsim-fpga-edition

Hence, we wanted to try out NVC - a relatively new opensource VHDL compiler (https://www.nickg.me.uk/nvc/index.html). While there are pre-built binaries for several OS there, we couldn't locate one for WSL - Windows + WSL running Ubuntu. So, we decided to build it from source - isn't it the best thing about opensource - build missing pieces yourself?  



So here is an Engineer's diary of how we got it up and running in less than 15 minutes! Fasten your seatbelt, off we go!

 Follow the below steps:

  • cd nvc-1.12.2
  • mkdir build
  • cd build/
  • sudo apt install llvm pkg-config libzstd-dev libdw-dev
  •  ../configure
  •  make
  •  sudo make install
Bingo! Off we go with NVC, try out a hello-world test generated via ChatGPT as below:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use std.textio.all;

entity hw is
end entity;

architecture Behavioral of hw is
begin
    process
        variable L : line;
    begin
        -- Write "Hello, World!" to the console
        write(L, string'("Hello, World!"));
        writeline(output, L);

        -- Stop simulation
        wait;
    end process;
end architecture;

Comments

Post a Comment

Popular posts from this blog

Don't go "wild" with Associative arrays in SystemVerilog - PySlint it!

Image
 Hash tables, modeled via Associative arrays is a powerful data structure in SystemVerilog. Python calls it as "dictionary". One of the "wild" features of SystemVerilog is that it allows associative arrays to be declared with arbitrary key type. An example:           class wild_c;             string wild_hash_table [*];           endclass : wild_c While the above is a legal SystemVerilog code, may even be seen as "easier" to write, it is bad from a reuse perspective. Some of the side effects (mostly bad) are: Unclear data structure to begin with - for writer and then the reader/maintainer of the code.  As the key can be anything, SV does not allow wildcard indexed associative array to be iterated via foreach loop. It cannot be passed as function parameter. Many find*  methods do not work on wild-card indexed associative arrays. For instance, find_first would need to return a queue of the keys, and when used on wild-card indexed array, it would be a queue o
Read more

Porting a complete UVC to Verilator + UVM - an anecdote!

Image
 So, here we are on Day-1 of UVM + Verilator becoming available to the public, start of democratizing chip design verification. In case you just woke-up/started on this topic, read the release of UVM + Verilator with some intricate details on the challenge on the way by Antmicro via:  https://antmicro.com/blog/2023/10/running-simple-uvm-testbenches-in-verilator/  Awesome work by the folks at Antmicro and fantastic support by the ecosystem specifically Western Digital, kudos!  At AsFigo , we are committed to fueling open-source driven chip design and verification. So we took this opportunity to port a commercial-grade UVC (Universal Verification Component or a Verification IP) and ported it to compile and run on Verilator. Below are our reflections from this experiment. Get in touch with us to discuss how AsFigo can help your VIPs and testbenches to be ported to opensource EDA.  Case study: VLBus - a simple peripheral bus intended for write/read to configuration registers (like the pop
Read more

Opensource testbench generator for VHDL designs, OSVVM included!

Image
VHDL holds a prominent position in the world of FPGA design, particularly within the military, aerospace, and defense sectors. It serves both as a Register Transfer Level (RTL) design language and as a tool for creating testbenches. The availability of open-source simulators, such as GHDL and NVC, alongside numerous free FPGA simulators and synthesis tools, has provided FPGA designers with a significant advantage over their SystemVerilog counterparts. While the Universal Verification Methodology (UVM) is widely adopted among SystemVerilog users, VHDL practitioners have traditionally relied on various homegrown methodologies and frameworks. Recently, however, off-the-shelf methodologies and frameworks such as OSVVM, UVVM, and VUnit have become available to VHDL users. Each of these options presents different levels of complexity, allowing users to choose the one that best meets their needs. Despite these advancements, the development of open-source utility tools supporting the latest me
Read more