Opensource testbench generator for VHDL designs, OSVVM included!

VHDL holds a prominent position in the world of FPGA design, particularly within the military, aerospace, and defense sectors. It serves both as a Register Transfer Level (RTL) design language and as a tool for creating testbenches. The availability of open-source simulators, such as GHDL and NVC, alongside numerous free FPGA simulators and synthesis tools, has provided FPGA designers with a significant advantage over their SystemVerilog counterparts.

While the Universal Verification Methodology (UVM) is widely adopted among SystemVerilog users, VHDL practitioners have traditionally relied on various homegrown methodologies and frameworks. Recently, however, off-the-shelf methodologies and frameworks such as OSVVM, UVVM, and VUnit have become available to VHDL users. Each of these options presents different levels of complexity, allowing users to choose the one that best meets their needs.

Despite these advancements, the development of open-source utility tools supporting the latest methodologies like OSVVM and VUnit has not kept pace. At AsFigo, we have noticed an increasing demand from customers for such utilities, especially following the rise of tools like Slang/PySlang and PySlint/UVMLint for SystemVerilog testbenches. Fortunately, there are now several Python-based parsers available for VHDL, each at different stages of maturity.

One such parser is a lightweight, Python-based tool known as VHLD_Parse (soon to be renamed VHDL_parse, as indicated here: VHDL_parse GitHub Issue).

To demonstrate its capabilities, let's consider a ubiquitous counter design example:

What if you were to create a testbench from scratch for a DUT like that say with OSVVM support? Few bells and whistles to start with:

• You need a clock (or two, maybe three?) - with some flexibility
• You most likely require a flexible reset generator
• A test controller
• Logging mechanism
• A barrier to prevent overruns (aka watchdog)
• DUT instantiation - that boring, error-prone, mundane typing work
• Stimulus, checking, coverage and more

So here is how our opensource TBGen would leverage OSVVM and do it for you. 

Starting with some basic infrastructure knobs:

Now, the DUT port automation:

Now the clock, reset generators - thanks to OSVVM utilPkg:

All of the above and more with a single command as:

python3 ../py_src/af_gen_tb.py -i ../dut_src/af_up_dn_counter.vhdl --osvvm

 Coming soon to theaters near you, through GitHub! Stay tuned to AsFigo www.asfigo.com 

This example showcases how simple Python-based utilities can be effectively utilized in VHDL projects. As the VHDL community continues to grow and evolve, tools like these will play an increasingly important role in streamlining the design and verification process.

Contact us to see how you can leverage our worldwide resources to shorten your VHDL design and verification challenges using innovative technologies.