Don't go "wild" with Associative arrays in SystemVerilog - PySlint it!

 Hash tables, modeled via Associative arrays is a powerful data structure in SystemVerilog. Python calls it as "dictionary". One of the "wild" features of SystemVerilog is that it allows associative arrays to be declared with arbitrary key type. An example:

        class wild_c;

          string wild_hash_table [*];

        endclass : wild_c

While the above is a legal SystemVerilog code, may even be seen as "easier" to write, it is bad from a reuse perspective. Some of the side effects (mostly bad) are:

  • Unclear data structure to begin with - for writer and then the reader/maintainer of the code. 
  • As the key can be anything, SV does not allow wildcard indexed associative array to be iterated via foreach loop.
  • It cannot be passed as function parameter.
  • Many find* methods do not work on wild-card indexed associative arrays. For instance, find_first would need to return a queue of the keys, and when used on wild-card indexed array, it would be a queue of "mixed key types", SystemVerilog does not support such queues.
Good news is, PySlint catches such usage and flags it really fast, see a sample below:


So, pull it from PySlint and deploy today!


Comments

  1. AsFigoDecember 11, 2023 at 7:47 AM

    This comment has been removed by the author.

    ReplyDelete
  2. AsFigoDecember 11, 2023 at 7:52 AM

    Good point by Ben Cohen on what's next step - please use a defined datatype as index such as int.
    int my_hash_table [int];

    ReplyDelete

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