PySlint - a modern approach to "on-demand" linting for Testbenches, SVA, Coverage Models and RTL code

 

Linting is a well-known, popular technique in large code development projects. Software engineers have been using Lint based rule checking to maintain high quality code adhering to a set of predefined coding guidelines. In hardware design field, Lint tools have been very popular in RTL design phase and designers use lint to ensure the design is synthesis friendly, DFT compliant etc.  Several popular coding guidelines have evolved over the last few decades such as Reuse Methodology Manual (RMM), Japan’s STARC standard etc. Often tools group a set of rules and create policies to ensure design code is RMM compliant etc. Verification on the other hand does not enjoy the same level of lint tools.  ensure that SystemVerilog is well established as the design verification language in semiconductor design flow. While rule checking (a la Linting) is well established for synthesizable code well over a decade, the verification counterpart lacked such technology in the past. With software giants such as Google, Meta investing in this domain, many fully featured parsers are now available, many as open source as well. In this paper, authors share their experiences in developing a highly customizable linter for SystemVerilog testbench code based on open source pyslang API.  Verification methodologies such as UVM have evolved over last decade and more and have provided much more than just guidelines including base class libraries, applications, examples etc. While there are no read-made/standard rule policies for coding guidelines available for verification (unlike in design), many customers tend to develop their own rules/policies primarily based on UVM and picking important ones as they deem fit for their projects. However, in the past there was no easy way of adhering to those rules and flagging any potential violations – thereby affecting quality, reusability aspects of codebase.

So, we introduce PySlint - a Python based linter for SystemVerilog TestBenches (TB), Assertions (SVA), Functional Coverage (FCOV) and of-course for RTL. idea is to provide sample code via public, free Python code base and enable end users to innovate from there on! 


We don't intend to sell PySlint as a tool - rather it is a platform to innovate, and all are welcome! 

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