VHDL Verification with OSVVM - ground-up approach

 If you use VHDL to design FPGA or ASIC (RTL design), it is likely that you have come across OSVVM - a methodology library and collateral that can significantly enhance productivity of VHDL testbenches. While there are quite a few conference papers and articles on OSVVM internals, here is our humble attempt to use it on a small design - ground-up. This is not a full-fledged demo of all OSVVM capabilities, rather a beginner's guide to the wonderful world of design verification with OSVVM. 

Before we go deeper into OSVVM, let's capture some common, protocol agnostic capabilities/features that every testbench would require: 

  • Clock generation, with bells and whistles to enable/disable etc.
  • Reset generation - with polarity control.
  • Scalable and flexible messaging features - to print progress during a running simulation and also being able to control it on a regression later in the game.
  • Watchdog - to alert those run-away simulations. 
  • Clear separation from TestBench (TB) to Testcase/Test Harness
  • PASS/FAIL indications at the end of a simulation
Let's see how OSVVM can help with each of these requirements:

Essentially, OSVVM provides a procedure named "CreateClock" that is handy. Below is what ChatGPT tells about this procedure:

In the given code, CreateClock is a procedure provided by the Osvvm.TbUtilPkg package, which is a part of the OSVVM (Open Source VHDL Verification Methodology) library. This procedure is used to generate a clock signal for simulation purposes in a testbench or test environment.

The CreateClock procedure has two parameters:

  • Clk: This is an output signal of type std_ulogic that represents the clock signal. The procedure generates a periodic waveform on this signal.

  • Period: This is a constant of type time that specifies the desired period of the clock waveform.

When the CreateClock procedure is called with the appropriate parameters, it generates a clock signal with the specified period. The generated clock waveform is used to drive the Clk signal in the testbench or test environment.

 For reset generation, use CreateReset procedure as below:


Leveraging on Generative AI to document this usage:

CreateReset is another procedure from the Osvvm.TbUtilPkg package, which is part of the OSVVM library. This procedure is used to generate a reset signal for simulation purposes in a testbench or test environment.

The CreateReset procedure has several parameters:

  • Reset: This is an output signal of type std_ulogic that represents the reset signal. The procedure generates a waveform on this signal to assert and deassert the reset condition.

  • ResetActive: This is a constant or a literal of type std_ulogic that specifies the active level of the reset signal. In the provided code, '1' is used, indicating an active-high reset.

  • Clk: This is the clock signal to which the reset signal is synchronized. It is of type std_ulogic.

  • Period: This is a constant of type time that specifies the desired period of the generated reset waveform.

  • tpd: This is a constant of type time that represents the desired delay from the start of the simulation until the reset signal is asserted.


For logging, use Log API as below:

    Log ("Start of test", ALWAYS);

 

A WatchDog process is shown below:




 This time, ChatGPT did not get the documentation for WaitForBarrier usage as above well enough, but with few prompts below is what got generated:

The WaitForBarrier procedure in the OSVVM library is used for synchronization purposes. It allows multiple processes to synchronize and proceed simultaneously at a designated synchronization point after a specified time duration has passed.

The WaitForBarrier procedure has the following parameters:

  • SyncBarrier: This is an input parameter of type Barrier that specifies the synchronization point where processes should wait.

  • Timeout: This is an input parameter of type Time that specifies the maximum time duration the processes should wait at the synchronization point before proceeding.


We will soon upload a simple, yet complete code for a LIFO design using OSVVM, so stay tuned!



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