AsFigo - enabling opensource chip design and verification.

AsFigo invites you to our next technical session, focused on enabling semiconductor design teams to adopt open-source EDA tools—especially for testbench linting workflows. Remote-dial-in link:  UVMLint meetup - Cambridge, June 27 | Meeting-Join | Microsoft Teams 📍 Event: UVMLint & SVALint – Enablers to Move Your Chip Design Ahead 📅 Date: Friday, June 27, 2025 🕙 Time: 10:00 AM to 12:00 Noon (UK Time) 📌 Location: Wellington House, East Road, Cambridge, CB1 1BH, United Kingdom ☎ Phone: +44 1223 451000 🌐 Format: Hybrid (in-person & remote via Microsoft Teams) 💡 Cost: Free (registration required - https://forms.gle/upzLGyWJbRnbgRzU7 ) After a successful SVALint session in Reading, UK, we’re bringing this discussion to Cambridge—one of the UK’s most active semiconductor hubs. This event is geared toward engineers working in UVM based verification, formal verification, and testbench architecture using UVM and SVA. Ag...

SVALint Technical Meetup – Hybrid Event in Reading, UK AsFigo invites engineers and verification professionals to a focused technical meetup on SVALint —an open-source static verification abstraction linting framework. The event takes place on Sunday, 8 June 2025 , from 15:00 to 18:00 BST , hosted in a hybrid format (face-to-face and online). Register via:  https://forms.gle/qo8TBczXjNk62yAP6   Venue (In-Person) Meeting Room-5, First floor,  Novotel Reading Centre 25B Friar Street – RG1 1DP, Reading – United Kingdom T +44 (0) 1189 522 610 novotel.com/5432 Virtual Attendance Join via Microsoft Teams Why SVA Linting? SystemVerilog Assertions (SVA) play a critical role in ensuring correctness in complex verification environments. However, poorly structured assertions can hurt simulation performance, complicate debugging, or lead to ambiguous semantics. Linting SVAs helps catch such issues early—enforci...

Open Source Chip Design & Verification Event – Chennai 2025 Open Source Chip Design & Verification Event – Chennai 2025 The open-source hardware movement is shaping the future of semiconductor innovation, and you’re invited to be part of it! Join us at the Open Source Chip Design and Verification Event – Chennai 2025 , where experts in the field will share insights on open silicon, FPGA development, and SystemVerilog tooling. 📅 Date: April 5th, 2025 ⏰ Time: 3:00 PM – 5:00 PM 📍 Venue: Object Automation System Solutions Inc., Chennai Speakers Srinivasan Venkataramanan (AsFigo, UK)  – svck: A Lightweight and Extensible SystemVerilog Linter Kirupanithi RP (Object Automation) – Building Custom Chips with OpenPOWER Hemamalini Sundaram (VerifWorks) – UVMLint - case studies VP Sampath Ram (Bharath Semiconductor Society) – FPG...

Writing clean, maintainable, and consistent SystemVerilog testbench code is crucial for efficient verification. While functional correctness is the ultimate goal, enforcing coding styles helps improve readability, collaboration, and long-term maintainability. A well-structured codebase also reduces debugging time and ensures better reuse across projects. The Need for Linting and Style Enforcement Linting tools help enforce best practices by catching stylistic and structural violations early. Some fundamental style checks for SystemVerilog testbenches include: Encapsulation : Ensure proper use of class , local , protected , and virtual keywords to promote modularity. Line Length : Keep lines within a readable limit (e.g., 100 characters) to improve readability. Avoid Global Variables : Minimize or eliminate the use of global variables to prevent unintended side effects. Consistent Indentation and Naming : Follow a uniform inde...

Unlocking RTL Quality with Open Source Technologies: A Must-Attend Event for Chip Designers In the ever-evolving world of chip design, verification bottlenecks and RTL quality remain critical challenges. Open-source tools and AI-driven approaches are revolutionizing the way we optimize and validate hardware designs. Join us for an exciting technical event that brings together industry experts, FPGA specialists, and innovators who are pushing the boundaries of open-source EDA. Why Attend? This event is designed for verification engineers, FPGA designers, and AI-driven hardware developers eager to explore new methodologies in SystemVerilog linting, FPGA coding best practices, and AI applications in chip design. Agenda Highlights (IST - India, UTC +5:30) 2:00PM - 2:30PM SV Testbench Constraints Can Blind You – Build Your Guards - Nambi JU, CTO, Lyle Technologies ...

The semiconductor industry is undergoing a transformation, with open-source tools playing a pivotal role in shaping the future of chip design and verification. On January 30, 2025 , AsFigo and VerifWorks will host the Open Source Chip Design and Verification Event , a hybrid event offering a platform to explore how open-source technologies are driving innovation in the semiconductor industry. 📅 Event Details Date: January 30, 2025 Time: 2:00 PM to 5:00 PM Location: Virtual (via MS Teams) This event will focus on the application of open-source tools for front-end design and verification in semiconductor chip development. The sessions will explore tools, techniques, and real-world applications that leverage open-source solutions to improve the quality and efficiency of chip design and verification workflows. 📋 Agenda The event features key speakers from various d...