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Linting SystemVerilog Testbench Code: Why Style Matters and Where Regex Falls Short

Writing clean, maintainable, and consistent SystemVerilog testbench code is crucial for efficient verification. While functional correctness is the ultimate goal, enforcing coding styles helps improve readability, collaboration, and long-term maintainability. A well-structured codebase also reduces debugging time and ensures better reuse across projects. The Need for Linting and Style Enforcement Linting tools help enforce best practices by catching stylistic and structural violations early. Some fundamental style checks for SystemVerilog testbenches include: Encapsulation : Ensure proper use of class , local , protected , and virtual keywords to promote modularity. Line Length : Keep lines within a readable limit (e.g., 100 characters) to improve readability. Avoid Global Variables : Minimize or eliminate the use of global variables to prevent unintended side effects. Consistent Indentation and Naming : Follow a uniform inde...
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Unlocking RTL Quality with Open Source Technologies - online event!

Unlocking RTL Quality with Open Source Technologies: A Must-Attend Event for Chip Designers In the ever-evolving world of chip design, verification bottlenecks and RTL quality remain critical challenges. Open-source tools and AI-driven approaches are revolutionizing the way we optimize and validate hardware designs. Join us for an exciting technical event that brings together industry experts, FPGA specialists, and innovators who are pushing the boundaries of open-source EDA. Why Attend? This event is designed for verification engineers, FPGA designers, and AI-driven hardware developers eager to explore new methodologies in SystemVerilog linting, FPGA coding best practices, and AI applications in chip design. Agenda Highlights (IST - India, UTC +5:30) 2:00PM - 2:30PM SV Testbench Constraints Can Blind You – Build Your Guards - Nambi JU, CTO, Lyle Technologies ...
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Open Source Chip Design and Verification Event: Unlocking the Future of Semiconductor Innovation

The semiconductor industry is undergoing a transformation, with open-source tools playing a pivotal role in shaping the future of chip design and verification. On January 30, 2025 , AsFigo and VerifWorks will host the Open Source Chip Design and Verification Event , a hybrid event offering a platform to explore how open-source technologies are driving innovation in the semiconductor industry. 📅 Event Details Date: January 30, 2025 Time: 2:00 PM to 5:00 PM Location: Virtual (via MS Teams) This event will focus on the application of open-source tools for front-end design and verification in semiconductor chip development. The sessions will explore tools, techniques, and real-world applications that leverage open-source solutions to improve the quality and efficiency of chip design and verification workflows. 📋 Agenda The event features key speakers from various d...
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AsFigo Instance Extraction Utility ($afPrHier)

The AsFigo Instance Extraction Utility ( $afPrHier ) is a Verilog Procedural Interface (VPI) app designed to automate the extraction of instance hierarchy data in Verilog simulations. It provides an efficient solution for analyzing and documenting the structural organization of Verilog designs, particularly in complex simulations. Purpose and Benefits Objective $afPrHier simplifies the process of collecting and documenting hierarchical relationships among modules and their instances in a Verilog simulation. It automates this task to reduce manual effort and potential errors. Features Automated Hierarchy Extraction: Gathers all module-instance relationships in a design and organizes them in a structured format. CSV-Based Reporting: Outputs hierarchy details in output_hier_info.csv with two essential columns: Module Name Instance Name ...
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WOSET 2024: Spotlight on yoYoLint - An Open-Source SystemVerilog RTL Linter

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As open-source electronic design automation (EDA) tools continue to grow in popularity, events like WOSET (Workshop on Open-Source EDA Technology) have become essential for showcasing community-driven advancements. The 2024 edition of WOSET features an exciting lineup, including yoYoLint—a new open-source SystemVerilog RTL linter designed for Yosys. Built on AsFigo’s innovative "Build Your Own Linter" (BYOL) model, yoYoLint adds a much-needed layer of quality control to open-source HDL flows, addressing the often-overlooked process of HDL linting. Understanding the Role of HDL Linting in EDA Linting is a critical phase in hardware description language (HDL) design flows, helping enforce design rules, style guides, and best practices to ensure code quality. A robust HDL linter for SystemVerilog helps identify errors early, such as unused variables, unsupported constructs, potential race conditions, or missing sensitivity list items, enabling teams to produce clean, consist...
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BYOL - a custom linter for Yosys; yoYoLint

yoYoLint is an opensource linter being developed to check SystemVerilog (SV) RTL code for compatibility with the Yosys open-source synthesis tool. Yosys, a popular, opensource  hardware description language (HDL) synthesis tool, has limited SystemVerilog support and often produces cryptic errors for unsupported constructs. As Yosys does not provide a comprehensive list of unsupported features, yoYoLint becomes essential in preemptively catching these issues before synthesis. Unlike off-the-shelf EDA tools, yoYoLint follows the BYOL (Build Your Own Linter) model, a concept proposed by AsFigo . This allows developers to customize and adapt the tool to their specific design needs and Yosys synthesis environment. Key Features Yosys-Specific Checks: yoYoLint flags unsupported SystemVerilog features, such as complex data types, advanced procedural blocks, and unsupported constructs in Yosys. RTL-Focused: Ana...
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Bridging the Gap: When Formal Verification Catches What Simulation Misses

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In the intricate world of semiconductor design verification, the interplay between formal verification and simulation-based approaches continues to evolve. A recent case study highlights the complementary nature of these methodologies and underscores the importance of a comprehensive verification strategy. The Scenario During a routine IP verification using formal tools and SystemVerilog Assertions (SVA), a bug was uncovered that had previously eluded detection in subsystem-level simulation. This discovery prompted a deeper investigation into the verification process and the tools employed. Formal Verification's Unique Strength Formal verification's ability to exhaustively explore state spaces within specified bounds allowed it to uncover a corner case that simulation had missed. This strength stems from formal tools' capacity to: Examine all possible states and input combinations Operate without the need for specific test vectors Explore deep states that might be...
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