Posts

From Guesswork to Metrics: Measuring Constraint Complexity in SystemVerilog (Part 1)

🚀 Why Care About Constraint Complexity? In SystemVerilog, constraint blocks are a core part of constrained-random verification. As your testbenches scale up, these blocks can become: Hard to read Difficult to debug Slow to solve Prone to over- or under-constraining Yet most teams rely on intuition or manual review to judge constraint quality. What if we could measure complexity more objectively? This is where Halstead Complexity Metrics come in. 📐 What Are Halstead Metrics? Originally developed by Maurice Halstead in the 1970s for software code analysis, these metrics: Count operators and operands Compute values like: Volume (how much information the code conveys) Difficulty (how hard it is to understand) Effort (how much mental work is required) Estimated bugs (how likely the code is to be error-prone) They’ve been applied in languages like C/C++, Java, and P...
Post a Comment
Read more

Driving UVM Quality: Join Our Next UVMLint Meetup in Newbury - Jul 18, 2025

Following the positive reception and thoughtful engagement at our recent technical meetups in Reading and Cambridge , AsFigo is pleased to invite you to our next UVMLint Technical Meetup , taking place in Newbury — a region with a strong footprint in semiconductor design and verification. This free, hybrid event offers a focused technical forum for engineers seeking to enhance the quality and maintainability of their UVM environments through structured linting , metrics analysis , and practical methodology insights . 📍 Event Details Date: Friday, 18th July 2025 Time: 14:00 – 16:00 BST Venue: Oxford House, 12–20 Oxford Street, Newbury, Berkshire, RG14 1JB Meeting Room: Donnington Register at:   https://forms.gle/VCiVEiKgzKJgPiAD8  Remote Access:   Join the meeting now: https://teams.microsoft.com/l/meetup-join/19%3ameeting_OGNiY2RjYzEtNGI0OC00MDg3LTk2OGYtZGZiZWMzNTQyMGQ1%40thread.v2/0?context=%7b%22Tid%22%3a%22ce8c6d03-7521-4120-aa04-...
Post a Comment
Read more

Got SystemVerilog Testbench Code with UVM, SVA ? Let’s Lint It – For Free!

We're inviting all SystemVerilog developers to share their testbench code using #UVM and/or #SVA for a free lint-check as part of our upcoming technical meetup. ✅ Submit your repo path or URL ✅ We’ll run our lint tools on it ✅ Get a detailed report ✅ Your code might be featured in a live demo! 🗓️ Event: #UVMLint and #SVALint Meetup 📍 Location: Cambridge, UK (remote attendance available) 👥 113+ engineers already registered , and counting! Don’t miss the chance to get valuable insights into your testbench quality — from syntax to assertions to methodology compliance. Register now: https://lnkd.in/dW3nX_KC Join via:  UVMLint meetup - Cambridge, June 27 | Meeting-Join | Microsoft Teams   Special thanks to our collaborators: Ajeetha Kumari, Ben Cohen, Hemamalini Sundaram and the #AsFigo team. #SystemVerilog #UVM #SVA #Lint #EDA #Verification #OpenSource #Meetup
Post a Comment
Read more

Join Us in Cambridge - Advancing Chip Verification with UVMLint & SVALint

AsFigo invites you to our next technical session, focused on enabling semiconductor design teams to adopt open-source EDA tools—especially for testbench linting workflows. Remote-dial-in link:  UVMLint meetup - Cambridge, June 27 | Meeting-Join | Microsoft Teams 📍 Event: UVMLint & SVALint – Enablers to Move Your Chip Design Ahead 📅 Date: Friday, June 27, 2025 🕙 Time: 10:00 AM to 12:00 Noon (UK Time) 📌 Location: Wellington House, East Road, Cambridge, CB1 1BH, United Kingdom ☎ Phone: +44 1223 451000 🌐 Format: Hybrid (in-person & remote via Microsoft Teams) 💡 Cost: Free (registration required - https://forms.gle/upzLGyWJbRnbgRzU7 ) After a successful SVALint session in Reading, UK, we’re bringing this discussion to Cambridge—one of the UK’s most active semiconductor hubs. This event is geared toward engineers working in UVM based verification, formal verification, and testbench architecture using UVM and SVA. Ag...
Post a Comment
Read more

SVALint Technical Meetup – Reading, UK

SVALint Technical Meetup – Hybrid Event in Reading, UK AsFigo invites engineers and verification professionals to a focused technical meetup on SVALint —an open-source static verification abstraction linting framework. The event takes place on Sunday, 8 June 2025 , from 15:00 to 18:00 BST , hosted in a hybrid format (face-to-face and online). Register via:  https://forms.gle/qo8TBczXjNk62yAP6   Venue (In-Person) Meeting Room-5, First floor,  Novotel Reading Centre 25B Friar Street – RG1 1DP, Reading – United Kingdom T +44 (0) 1189 522 610 novotel.com/5432 Virtual Attendance Join via Microsoft Teams Why SVA Linting? SystemVerilog Assertions (SVA) play a critical role in ensuring correctness in complex verification environments. However, poorly structured assertions can hurt simulation performance, complicate debugging, or lead to ambiguous semantics. Linting SVAs helps catch such issues early—enforci...
Post a Comment
Read more

UVMLint user group at Chennai - Widened scope to OpenPOWER

Open Source Chip Design & Verification Event – Chennai 2025 Open Source Chip Design & Verification Event – Chennai 2025 The open-source hardware movement is shaping the future of semiconductor innovation, and you’re invited to be part of it! Join us at the Open Source Chip Design and Verification Event – Chennai 2025 , where experts in the field will share insights on open silicon, FPGA development, and SystemVerilog tooling. 📅 Date: April 5th, 2025 ⏰ Time: 3:00 PM – 5:00 PM 📍 Venue: Object Automation System Solutions Inc., Chennai Speakers Srinivasan Venkataramanan (AsFigo, UK)  – svck: A Lightweight and Extensible SystemVerilog Linter Kirupanithi RP (Object Automation) – Building Custom Chips with OpenPOWER Hemamalini Sundaram (VerifWorks) – UVMLint - case studies VP Sampath Ram (Bharath Semiconductor Society) – FPG...
Post a Comment
Read more

Linting SystemVerilog Testbench Code: Why Style Matters and Where Regex Falls Short

Writing clean, maintainable, and consistent SystemVerilog testbench code is crucial for efficient verification. While functional correctness is the ultimate goal, enforcing coding styles helps improve readability, collaboration, and long-term maintainability. A well-structured codebase also reduces debugging time and ensures better reuse across projects. The Need for Linting and Style Enforcement Linting tools help enforce best practices by catching stylistic and structural violations early. Some fundamental style checks for SystemVerilog testbenches include: Encapsulation : Ensure proper use of class , local , protected , and virtual keywords to promote modularity. Line Length : Keep lines within a readable limit (e.g., 100 characters) to improve readability. Avoid Global Variables : Minimize or eliminate the use of global variables to prevent unintended side effects. Consistent Indentation and Naming : Follow a uniform inde...
Post a Comment
Read more