AsFigo - enabling opensource chip design and verification.

 If you use VHDL to design FPGA or ASIC (RTL design), it is likely that you have come across OSVVM - a methodology library and collateral that can significantly enhance productivity of VHDL testbenches. While there are quite a few conference papers and articles on OSVVM internals, here is our humble attempt to use it on a small design - ground-up. This is not a full-fledged demo of all OSVVM capabilities, rather a beginner's guide to the wonderful world of design verification with OSVVM.  Before we go deeper into OSVVM, let's capture some common, protocol agnostic capabilities/features that every testbench would require:  Clock generation, with bells and whistles to enable/disable etc. Reset generation - with polarity control. Scalable and flexible messaging features - to print progress during a running simulation and also being able to control it on a regression later in the game. Watchdog - to alert those run-away simulations.  Clear separation from TestBench (TB) ...

Consider an AI (Artificial Intelligence) engine trying to decipher key information from a series of images in real-time. Fourier transform is a powerful tool used to analyze and manipulate images in the frequency domain. The Fourier transform of an image result in a complex-valued representation, consisting of real and imaginary components. To visualize the frequency content of the image or perform further analysis, it is common to calculate the magnitude of this complex representation. This is done by computing the square-root ( sqrt ) of the sum of the squares of its real and imaginary components. By applying the sqrt function to the complex image representation, we can obtain the magnitude image. At system level, Matlab is commonly used to model such algorithms. Matlab's sqrt  works with both positive and negative numbers, which is different from a typical IEEE 754 standard. While SystemVerilog has a built-in system function $sqrt()  - it works only with scalars and does no...

  Think of noise filtering algorithms, floating point computations etc. - a handy operator in such circumstances is   modulo  - loosely defined as a function that returns remainder after division (however, there is a close cousin   rem  - for later discussion).  System designers often use   mod  function to perform certain periodic functions, DSP algorithms etc. When such systems are implemented in hardware, designers often use Verilog to capture the same intent. Verilog (or SystemVerilog) has   %  operator in-built to provide basic support for modulo computation - it works just fine for unsigned integers. However, in behavioral models, testbenches and AMS models, often real numbers get involved and suddenly you get an error from your favorite HDL simulator as below (Verilator as example): %Error: t.sv:7:32: Expected integral (non-real) input to MODDIV : ... In instance m 7 | $display ("3.2 MOD 1: %f", 3.2%1...

 Chip design industry is the key enabler for many of the modern-day electronic devices that we use day to day. Very likely, you are reading this very article on a device that has multiple "chips" (or integrated circuits/ICs) built using various techniques. Mathematical models are central to these systems especially in domains such as Biomedical engineering, automotive, 5G, etc. System Designers typically capture such models using MATLAB©, Octave, etc. These models leverage a rich set of functions built-in as part of these tools. Developing hardware designs is a niche skill set with SystemVerilog and UVM being used mostly to verify such designs prior to "production en masse”. MathLib is a library of mathematical functions similar to those available with Matlab/Octave but implemented in native SystemVerilog. With MathLib, once can run higher level reference models erstwhile coded in Matlab language in native SystemVerilog. This leads to direct cost saving for chip des...