AsFigo - enabling opensource chip design and verification.

We're inviting all SystemVerilog developers to share their testbench code using #UVM and/or #SVA for a free lint-check as part of our upcoming technical meetup. ✅ Submit your repo path or URL ✅ We’ll run our lint tools on it ✅ Get a detailed report ✅ Your code might be featured in a live demo! 🗓️ Event: #UVMLint and #SVALint Meetup 📍 Location: Cambridge, UK (remote attendance available) 👥 113+ engineers already registered , and counting! Don’t miss the chance to get valuable insights into your testbench quality — from syntax to assertions to methodology compliance. Register now: https://lnkd.in/dW3nX_KC Special thanks to our collaborators: Ajeetha Kumari, Ben Cohen, Hemamalini Sundaram and the #AsFigo team. #SystemVerilog #UVM #SVA #Lint #EDA #Verification #OpenSource #Meetup

AsFigo invites you to our next technical session, focused on enabling semiconductor design teams to adopt open-source EDA tools—especially for testbench linting workflows. 📍 Event: UVMLint & SVALint – Enablers to Move Your Chip Design Ahead 📅 Date: Friday, June 27, 2025 🕙 Time: 10:00 AM to 12:00 Noon (UK Time) 📌 Location: Wellington House, East Road, Cambridge, CB1 1BH, United Kingdom ☎ Phone: +44 1223 451000 🌐 Format: Hybrid (in-person & remote via Microsoft Teams) 💡 Cost: Free (registration required - https://forms.gle/upzLGyWJbRnbgRzU7 ) After a successful SVALint session in Reading, UK, we’re bringing this discussion to Cambridge—one of the UK’s most active semiconductor hubs. This event is geared toward engineers working in UVM based verification, formal verification, and testbench architecture using UVM and SVA. Agenda Highlights Upgrading to IEEE 1800.2 UVM with linting-guided workflows Using ...

SVALint Technical Meetup – Hybrid Event in Reading, UK AsFigo invites engineers and verification professionals to a focused technical meetup on SVALint —an open-source static verification abstraction linting framework. The event takes place on Sunday, 8 June 2025 , from 15:00 to 18:00 BST , hosted in a hybrid format (face-to-face and online). Register via:  https://forms.gle/qo8TBczXjNk62yAP6   Venue (In-Person) Meeting Room-5, First floor,  Novotel Reading Centre 25B Friar Street – RG1 1DP, Reading – United Kingdom T +44 (0) 1189 522 610 novotel.com/5432 Virtual Attendance Join via Microsoft Teams Why SVA Linting? SystemVerilog Assertions (SVA) play a critical role in ensuring correctness in complex verification environments. However, poorly structured assertions can hurt simulation performance, complicate debugging, or lead to ambiguous semantics. Linting SVAs helps catch such issues early—enforci...