AsFigo - enabling opensource chip design and verification.

Unlocking RTL Quality with Open Source Technologies: A Must-Attend Event for Chip Designers In the ever-evolving world of chip design, verification bottlenecks and RTL quality remain critical challenges. Open-source tools and AI-driven approaches are revolutionizing the way we optimize and validate hardware designs. Join us for an exciting technical event that brings together industry experts, FPGA specialists, and innovators who are pushing the boundaries of open-source EDA. Why Attend? This event is designed for verification engineers, FPGA designers, and AI-driven hardware developers eager to explore new methodologies in SystemVerilog linting, FPGA coding best practices, and AI applications in chip design. Agenda Highlights (IST - India, UTC +5:30) 2:00PM - 2:30PM SV Testbench Constraints Can Blind You – Build Your Guards - Nambi JU, CTO, Lyle Technologies ...

The semiconductor industry is undergoing a transformation, with open-source tools playing a pivotal role in shaping the future of chip design and verification. On January 30, 2025 , AsFigo and VerifWorks will host the Open Source Chip Design and Verification Event , a hybrid event offering a platform to explore how open-source technologies are driving innovation in the semiconductor industry. 📅 Event Details Date: January 30, 2025 Time: 2:00 PM to 5:00 PM Location: Virtual (via MS Teams) This event will focus on the application of open-source tools for front-end design and verification in semiconductor chip development. The sessions will explore tools, techniques, and real-world applications that leverage open-source solutions to improve the quality and efficiency of chip design and verification workflows. 📋 Agenda The event features key speakers from various d...