AsFigo - enabling opensource chip design and verification.

The AsFigo Instance Extraction Utility ( $afPrHier ) is a Verilog Procedural Interface (VPI) app designed to automate the extraction of instance hierarchy data in Verilog simulations. It provides an efficient solution for analyzing and documenting the structural organization of Verilog designs, particularly in complex simulations. Purpose and Benefits Objective $afPrHier simplifies the process of collecting and documenting hierarchical relationships among modules and their instances in a Verilog simulation. It automates this task to reduce manual effort and potential errors. Features Automated Hierarchy Extraction: Gathers all module-instance relationships in a design and organizes them in a structured format. CSV-Based Reporting: Outputs hierarchy details in output_hier_info.csv with two essential columns: Module Name Instance Name ...

As open-source electronic design automation (EDA) tools continue to grow in popularity, events like WOSET (Workshop on Open-Source EDA Technology) have become essential for showcasing community-driven advancements. The 2024 edition of WOSET features an exciting lineup, including yoYoLint—a new open-source SystemVerilog RTL linter designed for Yosys. Built on AsFigo’s innovative "Build Your Own Linter" (BYOL) model, yoYoLint adds a much-needed layer of quality control to open-source HDL flows, addressing the often-overlooked process of HDL linting. Understanding the Role of HDL Linting in EDA Linting is a critical phase in hardware description language (HDL) design flows, helping enforce design rules, style guides, and best practices to ensure code quality. A robust HDL linter for SystemVerilog helps identify errors early, such as unused variables, unsupported constructs, potential race conditions, or missing sensitivity list items, enabling teams to produce clean, consist...