AsFigo - enabling opensource chip design and verification.

Introduction to MSIE Multi-Snapshot Incremental Elaboration (MSIE, Copyright Cadence Design Systems) is a powerful feature of Cadence Xcelium that optimizes the verification process for digital designs by enabling incremental changes to be elaborated without needing to re-elaborate the entire design. This approach significantly reduces the time required for compiling and elaborating designs, making verification faster and more efficient. Typical simulation flow (without MSIE)  The below figure depicts a traditional approach to running test scenarios in a design and verification environment.   Each scenario involves three stages:  Compilation of the environment (testbench + DUT),  Elaboration of the compiled environment,  and Simulation of the elaborated environment.  This sequential process is repeated for each test scenario. How MSIE Works Primary and Incremental Snapshots: MSIE works by creating pre-elaborated snapshots of the design and testbench environme

In VHDL-based digital design, ensuring that every key aspect of your design is tested comprehensively is critical. Functional coverage plays a pivotal role in this process by quantifying how thoroughly the testbench exercises the design's functionality. In this article, we will demonstrate how to create a functional coverage model for a simple up/down counter ( af_up_dn_counter ) using BenchBot, a Python tool for generating templated testbenches, in conjunction with OSVVM (Open Source VHDL Verification Methodology), which provides a robust functional coverage package. Setting Up the Testbench with BenchBot BenchBot, a Python app simplifies the creation of VHDL testbenches by generating template files.  It serves as a starting point rather than a fully functional testbench with all tests. However, it goes way beyond basic testbench by creating functional coverage model for all relevant DUT ports.  We will show an example of this below. Overview of the Design The design under