AsFigo - enabling opensource chip design and verification.

ModelSim - Intel FPGA Edition is a powerful simulation tool designed for FPGA design verification. It offers comprehensive simulation capabilities, supporting both Linux and Windows platforms. The Starter Edition is available for free installation without a license, making it accessible for a wide range of users. https://www.intel.com/content/www/us/en/software-kit/750666/modelsim-intel-fpgas-standard-edition-software-version-20-1-1.html If you are on a CentOS (7/8) 64-bit machine, chances are that you get weird errors while running vlib/vlog/vcom/vsim commands after installation. Below is how our team recently fixed it for a local FPGA house.  Below are the steps to get all necessary packages installed. Given the nature of Linux in general - your mileage may vary, we would love to hear in comments below if you find this useful, any more errors that you encountered during this installation etc.  ModelSim - Intel FPGA Edition may not run on CentOS 7 because it is a 32-bit application, a

 YAML, which stands for "YAML Ain't Markup Language," is a human-readable data serialization standard that is ideal for configuration files. We at AsFigo are helping customers adopt YAML for documenting VHDL (VHSIC Hardware Description Language) designs, especially at the interface level. One of the primary benefits of using YAML for VHDL designs is that it makes the information easier to parse and modify. This structured format allows for straightforward code generation and updates, significantly improving workflow efficiency. With YAML, you can create an organized, easy-to-read representation of VHDL entity interfaces, detailing ports, libraries, and other configurations. This structured approach not only aids developers in understanding and managing complex designs but also facilitates tool integration.   Below is a simple example YAML for a trivial up-down counter: Take a look at our opensource OSVVM Testbench generator project that utilizes this idea at: https://gith

During a recent conversation with a PhD student in the USA, our team highlighted some of our team's recent work in promoting opensource EDA tools for SystemVerilog Assertions (SVA). Below is an excerpt from that conversation for wider audience. For opensource SVA tools, Verilator does have some support. We have released  SVA for APB - running in Verilator:  https://github.com/AsFigo/af_ sva_apb We presented this work at LatchUp 2023 event at Santa Barbara:  https://www.youtube. com/watch?v=vMscbHq1vd8   We also have developed an opensource linter for SV, SVA, DPI etc. see:  https://github.com/ AsFigo/pyslint

RISC-V – a name that sparks innovation all across the globe! Recent market survey by SHD indicates RISC-V industry to touch $92B by 2030 ( The SHD Group Has Released a Complimentary Version of the 2024 RISC-V Market Analysis Report Containing Current Market Data and Future Projections | Newswire ).  Credits: SHD We at AsFigo are driven by opensource and help our customer adopt the same in chip design. One challenge that many RISC-V verification teams are facing is the long coverage closure cycles at RTL stage. This is primarily due to the long simulation cycles when RTL along with RISC-V assembly code is simulated using a typical event-driven simulator. We have recently helped customers with this challenge by leveraging on opensource RISCV-DV framework to measure functional coverage of uCode using ISS (Instruction Set Simulator) and also with a thin HDL-like testbench. Below is a summary of results of this approach. Do join us at RISC-V Summit Europe 2024 at Munich to learn more!

We at AsFigo AsFigo love Opensource. Off late we have been helping some European customers adopt modern verification techniques using VHDL. As a byproduct we have been building a Python based VHDL utility to generate a generic testbench based on OSVVM. While doing so, our team stumbled upon few subtle simulator issues, see: https://osvvm.org/forums/topic/sbrd-package-issue-with-modelsim-fpga-edition Hence, we wanted to try out NVC - a relatively new opensource VHDL compiler (https://www.nickg.me.uk/nvc/index.html). While there are pre-built binaries for several OS there, we couldn't locate one for WSL - Windows + WSL running Ubuntu. So, we decided to build it from source - isn't it the best thing about opensource - build missing pieces yourself?   So here is an Engineer's diary of how we got it up and running in less than 15 minutes! Fasten your seatbelt, off we go!  Follow the below steps: Grab the latest NVC tar ball from:  https://github.com/nickg/nvc/releases/ . In our