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Showing posts from July, 2025

From Guesswork to Metrics: Measuring Constraint Complexity in SystemVerilog (Part 1)

🚀 Why Care About Constraint Complexity? In SystemVerilog, constraint blocks are a core part of constrained-random verification. As your testbenches scale up, these blocks can become: Hard to read Difficult to debug Slow to solve Prone to over- or under-constraining Yet most teams rely on intuition or manual review to judge constraint quality. What if we could measure complexity more objectively? This is where Halstead Complexity Metrics come in. 📐 What Are Halstead Metrics? Originally developed by Maurice Halstead in the 1970s for software code analysis, these metrics: Count operators and operands Compute values like: Volume (how much information the code conveys) Difficulty (how hard it is to understand) Effort (how much mental work is required) Estimated bugs (how likely the code is to be error-prone) They’ve been applied in languages like C/C++, Java, and P...

Driving UVM Quality: Join Our Next UVMLint Meetup in Newbury - Jul 18, 2025

Following the positive reception and thoughtful engagement at our recent technical meetups in Reading and Cambridge , AsFigo is pleased to invite you to our next UVMLint Technical Meetup , taking place in Newbury — a region with a strong footprint in semiconductor design and verification. This free, hybrid event offers a focused technical forum for engineers seeking to enhance the quality and maintainability of their UVM environments through structured linting , metrics analysis , and practical methodology insights . 📍 Event Details Date: Friday, 18th July 2025 Time: 14:00 – 16:00 BST Venue: Oxford House, 12–20 Oxford Street, Newbury, Berkshire, RG14 1JB Meeting Room: Donnington Register at:   https://forms.gle/VCiVEiKgzKJgPiAD8  Remote Access:   Join the meeting now: https://teams.microsoft.com/l/meetup-join/19%3ameeting_OGNiY2RjYzEtNGI0OC00MDg3LTk2OGYtZGZiZWMzNTQyMGQ1%40thread.v2/0?context=%7b%22Tid%22%3a%22ce8c6d03-7521-4120-aa04-...