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Is your DPI-enabled SystemVerilog simulation running slow? Are you looking for ways to improve performance? Sometimes, a small remodelling of your DPI functions and using pure functions can help significantly. The Direct Programming Interface (DPI) allows SystemVerilog to interact with C code. Among the DPI constructs, pure functions are special because they are side-effect free and predictable. Using them correctly can improve simulation speed and reliability. However, SystemVerilog LRM imposes several subtle restrictions on imported pure  functions. Let's delve into one such nuance today a bit deeper! Referential Transparency Referential transparency is a concept from programming. An expression is referentially transparent if it can always be replaced by its value without changing the behaviour of the program. For example: The expression 2 + 3 can always be replaced with 5 . The expression rand() cannot, since each call may give a different result. In SystemVer...

Ensuring Correctness and Observability in SPI Signal Assertions In SPI verification, a fundamental requirement is that all active signals— SCLK , MOSI , and MISO —must be fully defined whenever chip-select is asserted . Any unknown or high-impedance state ( X or Z ) can compromise data integrity and lead to subtle bugs. SystemVerilog Assertions (SVA) offer a natural mechanism to codify this requirement. When applied thoughtfully, they enforce correctness and enhance diagnostic clarity. Clear, modular assertions make failures immediately understandable, particularly in larger testbenches, which aligns well with style-aware analysis tools. Issue 1: Functional Correctness A common misstep is to combine multiple signals in a single $isunknown call with a logical AND: // INCORRECT $isunknown(spiclk && mosi && miso) The problem: logical AND short-circuits evaluation, potentially masking unknown states. Example: spiclk = X, mosi = 0, miso = 1 spiclk ...

A solution‑first guide to preventing the classic dangling else error caused by UVM reporting macros. UVMLint Rule: No Trailing Semicolon After UVM Reporting Macros Define a lint rule that flags any UVM reporting macro invocation immediately followed by a semicolon. Implementation detail: This rule should be parser‑aware . Avoid pure regex; require an AST/token stream so comments, strings, and macro line breaks are handled correctly. Why This Rule Exists Consider a simple user code as below:  // Buggy code if (debug_on) `uvm_info("DEBUG", "state info", UVM_LOW); // semicolon here else $display("Doing something else"); The UVM BCL defines  `uvm_info  as a  complete  begin...end  block . Adding a semicolon after the macro turns into a null statement that terminates the  if  prematurely, leaving the  else  orphaned. // UVM BCL (abridged) `define uvm_info(I...

Linting SystemVerilog and UVM testbench code is crucial to maintain quality and compatibility. Many teams start by writing quick regex or string-search scripts to catch problematic patterns—like deprecated variables, disallowed constructs, or outdated API usage. While regex-based linting can be tempting due to its simplicity, it often leads to false failures and missed issues because SystemVerilog’s syntax and preprocessing are too complex for simple text matching. In this series, we will explore common linting scenarios, we introduced this in an earlier post here:   https://asfigo.blogspot.com/2025/02/linting-systemverilog-testbench-code.html  Below is the next one in this series with a concrete example - detecting deprecated UVM constructs like uvm_top , and demonstrate why a proper parser-based approach using tools like Google’s Verible is superior. A Quick, regex style lint example When maintaining UVM code for compatibility, one common check is to detect the use of u...