Value of UVMLint - an anecdote from Race Conditions in UVM BCL code
Race conditions are one of the dreaded aspects of Verilog/SystemVerilog. Race conditions in SystemVerilog lead to unpredictable behavior due to competing threads or processes accessing shared resources without proper synchronization. Debugging race conditions is challenging due to their non-deterministic nature, which means issues may appear sporadically and be hard to reproduce, complicating the identification and resolution of the underlying problem. It gets compounded by the fact that different EDA tools can behave differently on your code (with race condition) and yet be 100% LRM compliant (meaning no one will fix it for you). Would you believe that up until recently, UVM Base Class Library (BCL) had potential race conditions deep inside? Hard to believe? See for yourself a report from IEEE 1800.2 UVM core team members: 08376: 'static const xx ' class members with initialization - Accellera Mantis (mantishub.io) Understanding Race Conditions in UVM: Why Switching fr