AsFigo - enabling opensource chip design and verification.

Universal Verification Methodology (UVM) stands as the pinnacle of design verification methodologies in the ASIC and FPGA domain. The integration of linting and static code analysis has emerged as a vital practice, particularly in projects with broad user bases, extended lifetimes, and distributed development teams. Recently, during the UVM IEEE 1800.2-2023 release cycle (at DVCon US 2024), the potential for a custom UVMLint solution to enhance the UVM Base Class Library (BCL) development process was recognized. Some of the lead developers of UVM BCL suggested to create a simple rule deck that focuses on specific issues seen by the core development team over last few years than a general-purpose linter that may end up throwing 1000s of violations.   At AsFigo, we've taken the initiative to develop custom linting rules tailored specifically for the UVM BCL. Our goal is to offer our community an open-source lint package that can be used by the UVM IEEE committee and the wider devel...

              As verification engineers – we believe strongly in Trust-but-Verify mindset. So, as part of our #UVMLint value finding, we decided to run it on official examples shipped along with Accellera/IEEE UVM libraries. One of the most referred examples from UVM library is APB UVC/agent code: Usually, the intention of such examples is to serve as “golden reference” for users to model their verification environments. However, no lint checks were done (at least officially/publicly) on such examples shipped with UVM so far – partly due to non-availability of such UVMLint solutions, partly due to lack of commonly agreed rules etc. So with the opensource PySlint was built by AsFigo during 2023, goal was to fill this void and democratize UVMLint to the wider user base. Fast forward – Feb 2024, we ran UVMLint on these examples and below is what we found: While we ran a subset of rules on this small VIP/UVC, we are thrilled by the findings from UVMLi...